There exists a continuing need to improve semiconductor device performance and further scale semiconductor devices. These needs can be met by improvements in two broad categories; process and structure. Process improvements are those that allow the fabrication of devices and circuits with smaller dimensions in ever higher density, quantity and reliability. The structure improvements include new device designs that allow greater circuit performance, control and reliability.
As devices have continued to shrink and improve in performance, a number of characteristics have become important to further device scaling and performance improvement. One such characteristic is channel mobility, which is a factor in scalability and device performance. Channel mobility is electron and hole mobility through a channel region (source to drain) of a transistor. As devices continue to shrink in size, the channel region for transistors continues to also shrink in size. Such shrinkage can negatively impact channel mobility and lead to problems such as short channel effects.
As a result, improvements in channel mobility can lead to improvements in scaling and performance. One technique that may improve scaling limits and device performance is to introduce strain into the channel region, which can improve electron and hole mobility. Different types of strain, including biaxial tensile strain, uniaxial tensile strain, biaxial compressive strain, and unitaxial compressive strain, have been introduced to channel regions of various types of transistors in order to determine their affect on electron and/or hole mobility. For some devices, types of strain improve mobility whereas other degrade mobility.
A problem with applying strain to a semiconductor device is that the strain can improve performance for one type of device (e.g., PMOS) while at the same time degrading performance of another type of device (e.g., NMOS). As a result, tradeoffs are often made in conventional devices for performance of one type versus another.